1. Field of the Invention
The present invention relates to a ferroelectric memory utilizing ferroelectric capacitors and in particular relates to a ferroelectric memory wherein bit line capacitance can be optimized.
2. Description of the Related Art
Ferroelectric memories utilizing ferroelectric capacitors are widely employed in IC cards etc since they are non-volatile and are capable of high-speed writing and reading comparable with DRAMs. In such a ferroelectric memory device, data is stored and read by utilizing the hysteresis characteristic and residual polarization effect possessed by the ferroelectric films of ferroelectric capacitors. When writing, a ferroelectric capacitor is put in a polarized condition in one direction by applying an electrical field in one direction to the ferroelectric capacitor, or is put in a polarized condition in the opposite direction by applying an electrical field to the ferroelectric capacitor in the opposite direction. Such a polarized condition is maintained as residual polarization even after the electrical field that was applied to the ferroelectric capacitor is removed and so functions as non-volatile memory. On the other hand, when reading, the voltage of a bit line pair is changed by flowing out different amounts of charge from the capacitor to the bit line pair in accordance with the polarization condition of the ferroelectric capacitor and the minute voltage difference output to the bit line pair is detected by a sensing amplifier.
FIG. 1 is a circuit diagram of a typical prior art ferroelectric memory cell. The memory cell MC illustrated in the Figure is of so-called two-transistor, two-capacitor (2T2C) construction and comprises a pair of transistors Q1, Q2 and a pair of ferroelectric capacitors C1, C2 connected with these. The gates of transistors Q1, Q2 are connected with word line WL and, in addition, the source or drain electrodes of transistors Q1, Q2 are respectively connected with a pair of bit lines BL, /BL. In addition, ferroelectric capacitors C1, C2 are connected with plate line PL. Also, sensing amplifier SA is connected with bit line pair BL, /BL. Sensing amplifier SA comprises a pair of cross-connected CMOS inverters 10, 12 and activating transistors 13, 14 provided between these and power sources Vcc and Vss. When activating signals PSA, NSA are applied to activating transistors 13, 14, the sensing amplifier comprising the pair of CMOS inverters 10, 12 is activated so as to detect the voltage difference between bit line pair BL, /BL.
In writing, the pair of capacitors C1, C2 of memory cell MC are polarized in respectively opposite directions, to maintain the polarized condition. During reading, with word line WL raised, when plate line PL is first driven to H(High) level then returned to L(Low) level, a charge corresponding to the polarized condition of the pair of capacitors C1, C2 flows to bit lines BL, /BL, generating a minute voltage difference between the bit line pair. This voltage difference is detected by sensing amplifier SA.
FIG. 2 is a characteristic graph showing the relationship between the bit line capacitance and the voltage difference of a ferroelectric memory. The bit line capacitance CBL is shown along the horizontal axis and the voltage difference dVBL between the bit lines on reading is shown along the vertical axis. This characteristic shows that the bit line capacitance CBL has an optimum value Cx at which the voltage difference dVBL between the bit lines on reading is a maximum. In general, when the bit line capacitance becomes large, the change of voltage of the bit lines produced by the minute charge output from the memory cell on reading becomes small and the voltage difference dVBL between the bit lines becomes small. When the voltage difference between the bit lines becomes small, the detection margin of the sensing amplifier becomes small with the result that, in the worst case, reading may become impossible. Also, when the bit line capacitance becomes small, contrariwise, the voltage difference between the bit lines becomes larger, increasing the detection margin of the sensing amplifier.
A characteristic feature in FIG. 2 is, however, that, when the bit line capacitance CBL becomes smaller than the optimum value Cx, contrariwise, the voltage difference between the bit lines becomes smaller and the detection margin becomes smaller. The reasons for this are as follows. As described above, when reading, plate line PL is driven to H level from L level and the voltage of the bit line is raised by outputting to the bit line side a charge in accordance with the residual polarization condition of the cell capacitor at this point. Since the amounts of charge that are output to the bit lines differ in accordance with the residual polarization condition of the cell capacitors, a voltage difference is generated across the bit line pair. If therefore the bit line capacitance is too large, the change of bit line voltage produced by the charge flowing out from the cell capacitor becomes small.
However, if the bit line capacitance becomes very small, when the plate line PL is driven to H level, the voltage applied to the cell capacitor becomes small. The reason for this is that the voltage that is applied to the plate line PL (usually, power source voltage of 5V) is divided between the cell capacitor and the bit line capacitance, the divided voltage being applied to the cell capacitor. If the voltage that is applied to this cell capacitor is above the maximum voltage in the hysteresis characteristic of the ferroelectric material, the amount of charge flowing out from the cell capacitor becomes a maximum value. However, if the bit line capacitance becomes extremely small (or the cell capacitor capacitance becomes extremely large), causing the voltage applied to the cell capacitor to become less than the maximum voltage in the hysteresis characteristic of the ferroelectric material, the charge amount flowing out from the cell capacitor becomes smaller and contrariwise the voltage change of the bit line becomes smaller. As a result, a characteristic as shown in FIG. 2 is obtained.
Thus, when the bit line capacitance becomes smaller than optimum value Cx, the read margin decreases, which is undesirable. The bit line capacitance may become less than the optimum value Cx if, for reasons of the structure of the cell array, a construction is adopted in which the number of word lines is small so that the length of the bit lines in short. This tends to adversely affect the read margin, which is undesirable.
A special test for ferroelectric memory is a retention test, in which a check is made as to whether or not normal operation is retained in a condition in which the residual polarization of the ferroelectric capacitors is attenuated by putting the memory in a prescribed high-temperature condition. This test is time-consuming, since the memory must be held in a high temperature condition for a long time. Consequently, if there are a plurality of types of memory of different bit line capacitance, even if the characteristic variation is the same in the high temperature condition of the ferroelectric capacitors of the memories; the read margin will be different due to the difference of the bit line capacitances, so it will be necessary to perform a retention test in respect of all of the types of memory. If the bit line capacitance is the same for all types of memory, the read margin that is caused thereby will be the same, so a common retention test can be performed.
An object of the present invention is therefore to provide a ferroelectric memory wherein bit line capacitance can be optimized.
In order to achieve this object, according to one aspect of the present invention, in a ferroelectric memory, there are provided a plurality of word lines, a plurality of bit lines crossing there-with, a plurality of memory cells having ferroelectric capacitors arranged at the positions of these crossovers and a plurality of correction capacitors connectable with the bit lines. At least some of the plurality of correction capacitors are connected with a bit line so as to be capable of increasing bit line capacitance by a prescribed amount.
In an even more preferred embodiment, the correction capacitors are arranged in a twist region where the bit lines cross over. Or in another preferred embodiment, dummy capacitors of a dummy cell region formed at the periphery of a cell array having a plurality of memory cells are connected with the bit lines as correction capacitors. These correction capacitors are then suitably connected with the bit lines so as to make the bit line capacitances approach the optimum values. The number of correction capacitors connected is suitably selected. Also, this connection may be effected for example by the presence/absence of contact holes or the presence/absence of metal formation by the master slice method.
In another preferred embodiment, the correction capacitors are connected with the bit lines by switching means whose conduction is suitably controlled by means of a correction control signal. This correction control signal may for example be generated by setting in a register on power-on.